Interconnect requirements for the 22nm technology node and beyond, driven by shrinking FEOL geometry, push the limits of unit process tools for BEOL as well as FEOL. BEOL tools for WLCSP (Wafer level chip scale packaging) take advantage of many lithographic techniques utilized in the manufacture of the chip in the Front End of Line (FEOL).
One of the principal processes utilized in the back end of line is the Photolithographic process to perform such steps as redistribution layer, under bump metallization, and bump formation. An example of bump formation during the lift-off resist process is shown below:
Semiconductor photolithographic processing steps are discussed below.
Wafer Handling steps
- The substrate is automatically withdrawn from a cassette which may be in a SMIF pod. Alternatively for 300mm wafers a FOUP opener may be employed.
- The substrate is precisely positioned on a rotatable vacuum chuck such that the center of the substrate is coincident with the center of rotation of the vacuum chuck.
- After photoresist is applied the substrate is baked (normally on a heated plate provided for the purpose.)
- The substrate is returned to the cassette or to a second cassette.