The process of manufacturing semiconductors or integrated circuits (commonly called ICs or chips) typically consists of hundreds of steps, during which hundreds of copies of an integrated circuit are formed on a single wafer.
Generally, the process involves the creation of 8 to 20, and frequently more, patterned layers on (and into) the wafer, ultimately forming the complete integrated circuit. This layering process creates (interconnected) electrically active regions on the semiconductor wafer surface.
Silicon Wafer Manufacturing
Semiconductor manufacturing begins with production of the wafer, i.e., a thin, round slice of a semiconductor material varying in size 6 inches to 12 inches in diameter. The finished wafer is approximately 15 mil thick. The materials are primarily silicon; however, gallium arsenide, silicon carbide, germanium and others undergo similar processes. Purified polycrystalline silicon is created from sand, one of the most abundant materials available on our planet, is heated to a molten liquid. In a process similar to repeatedly dipping a wick in wax to make a candle, a small piece of solid silicon (seed) is dipped in molten liquid. As the seed is slowly withdrawn (by mechanical means) from the melt, the liquid quickly cools to form a single crystal ingot.
This cylindrical crystal ingot is then ground to a uniform diameter. A diamond saw blade slices the ingot into thin wafers. The cut wafers are then processed through a series of machines where they are ground (optically) smooth and chemically polished.
The wafers are now ready to be sent to the wafer fabrication area fab, where they are used as the foundation for manufacturing integrated circuits (ICs).
Wafer Fab Manufacturing
The heart of any semiconductor manufacturing business is the fab, where the integrated circuit is formed on the wafer. The fabrication process, which takes place in an environmentally controlled clean room, involves a series of principle repetitive steps described below. Typically, it takes from 10-30 days, and frequently much longer, to complete the fabrication process.
Thermal Oxidation-Wafers are pre-cleaned using high-purity deionized water and various low-particulate chemicals, a must for high-yield production. The silicon wafers are heated to approximately 1000 C and exposed to ultra-pure oxygen in the oxidation furnace. Under carefully controlled conditions, a silicon dioxide insulator film of uniform thickness is formed on the surface of the wafer.
Patterning-Masking is used to protect one area of the wafer while working on another. This process is referred to as photolithography. A photo resist, light-sensitive film is spin coated onto the wafer, giving it characteristics similar to a photographic film. A (micro) aligner aligns the wafer to a glass mask and then projects an intense ultraviolet light through the mask, exposing the photo resist with the mask pattern, thereby transferring the image from the mask into the light-sensitive film.
Etching-The wafer image is then developed (like a photo negative). The exposed photo resist is chemically removed and baked to harden the remaining photo resist pattern, which now is no longer light sensitive. It is then exposed to a chemical wet solution or plasma (gas discharge) so that areas not covered by the hardened photo resist are etched away. The remaining photo resist is now removed using either wet or plasma chemistry. The wafer is optically inspected to assure that the image transfer from the mask to the top silicon layer is correct, and then goes on to the next step.
Doping/Diffusion-Atoms with one less electron than silicon (such as boron) or one more electron than silicon (such as phosphorus) are introduced into the area exposed by the etch process, to alter the electrical character (conductivity) of the silicon. These areas are called P type or N type, respectively, which reflects their conducting characteristics.
Repeating the Above Steps-The thermal oxidation, masking, etching and doping steps are repeated many times until the last "front end" layer is completed (all active devices have been formed).
Dielectric Deposition and Metallization-Following completion of the "front end, " the individual devices are interconnected "backend" (like on a PC board) using a series of alternating metal depositions, dielectric films, with their respective patterning. Current semiconductor fabrication includes as many as 5 to 7 metal layers for logic, and fewer for memory, separated by dielectric layers (insulators).
Passivation-After the last metal is patterned, a final insulating layer (passivation) is deposited to protect the circuit from damage and contamination. Openings are etched in this film to allow access to the top metal later by electrical probes and subsequent wire bonds.
Electrical Test-An automatic, computer-driven test system checks for functionality of each chip on the wafer. Chips that do not pass the test are marked for automatic rejection. For simpler devices a mechanical probe is used.
Assembly-A diamond saw slices the wafer into single chips. Sizes can vary from 1 x 1 mm to 10 x 10 mm. The rejected chips are discarded and the remaining chips are visually inspected under a high-power microscope before packaging.
Each chip is then assembled into an appropriate package that provides the contact leads for the chip. In one type of interconnect a wire bonding machine attaches wires, a fraction of the width of a human hair, to the leads of the package. The packaged chip is tested again prior to delivery to the customer. Alternative, the chip can be assembled in a ceramic package for certain high performance applications.