There is currently a general consensus among industry analysts, investors, and company executives that leading edge digital chip development projects costs $30-$100M to develop. This negative view of chip development costs has led to severely decimated levels of VC investments and has even led to certain companies scrapping whole products lines. Today’s chips have a bigger impact on the world’s economy than ever and reduced investments in chip product development will eventually have a very negative impact on the economy. China for one has realized this and is pouring billions of dollars into their local semiconductor economy. This article will go through some of the reported data and show that present assumptions regarding chip development costs are very much exaggerated and that it is possible to design state of the art chips at a fraction of the cost previously reported.
Why is Chip Development so Expensive?
Chip development has never been cheap and there is no question that it’s getting more expensive. The million dollar question is: “how much more expensive?” The consensus among industry pundits is that there is no way to do a leading edge chip with less than $30-$100M.[3-4] Let’s take a look at some of the most common arguments for the “exponential” increase in chip development costs.
“Mask costs are increasing exponentially!”
It used to be that you could design a product with production mask costs in the range of $100K. Today, production mask costs at leading nodes can cost $1-2M. This has the effect of increasing the minimum market size that is practical to address with a leading edge chip design. Still, given a decent size market or high chip selling prices, mask costs are certainly not show stoppers and don’t explain the $100M price tag.
“EDA tools are getting really expensive!”
While EDA tools are certainly not cheap, aggressive volume purchasing agreements, increased feature integration and increased efficiency in the tools have made today’s tools far more cost effective than those of ten years ago. Today many leading chips can be taped out using vanilla flows derived from reference scripts provided by the EDA vendor. Thus, per transistor and per project, the cost of EDA tools has actually gone down in the last ten years.
“Deep submicron design is really hard!”
Chip design is certainly getting more difficult as we move to finer process geometries. At 0.35um and above, life was simple. Gates were slow, wires were fast, and there was virtually no leakage to speak of. The only problem was that chips were slow, power hungry, and big! Since then, the design constraints and difficulties have been piling on with every process node. In order of introduction designers had to learn and deal with: wire delays, voltage drops, signal integrity, leakage, process engineering effects like stress, and most recently on chip variability and an explosion in the number and complexity of device design rules. The introduction of each one of these effects was painful, but within one process generation, the EDA industry always seemed to find automated methods of dealing with them, thus keeping engineering team growth to a minimum. Deep submicron chip design is definitely not for hobbyists, but for a small expert team equipped with state of the art tools, it is today possible to accomplish in weeks what used to take a generously sized team 6-9 months. 
“Chips are getting incredibly complex!”