The thermal performance of semiconductor devices is most often specified according to JEDEC standards JESD51 1-14 which describes precisely how various steady-state thermal metrics are to be measured. Most of these metrics represent a thermal resistance between the junction of a semiconductor and some reference; e.g. Rth-JA (Junction-to-ambient), Rth-JB (Junction-to-board), or Rth-JC (Junction-to-case). However all of the above thermal metrics characterize the steady-state behavior and have been designed for semiconductors with a single heat source only. While the extension of a stationary thermal resistance Rth-JX to the corresponding transient thermal impedance th-JX is straightforward the adaptation of existing standards for the characterization of devices with multiple heat sources is far less obvious. This publication gives an overview on the theoretical framework which allows extending the existing thermal metrics in a compliant way. We demonstrate the method utilized for thermal impedance matrix measurements and show how thermal surroundings affect the thermal relations inside the package.
- Transient thermal impedance matrix;
- Multiple heat sources;
- Multichip structures